Wiring Board and Semiconductor Device

ABSTRACT

There is disclosed a wiring board comprising a core substrate  110 , a build-up layer  130   a  formed on at least one side of main surfaces the core substrate, wherein a cavity  120  for accommodating a chip-type decoupling capacitor  121  is formed in the build-up layer  130   a . The capacitor  121  includes electrode terminals on an upper surface thereof that are directly connected to a semiconductor component, and electrode terminals on a back surface of the capacitor  121  is connected to a wiring conductor layer  132   a  on a bottom surface of the cavity  120 . This structure enables decoupling capacitor and the semiconductor component  260  to be connected with low resistance and low inductance.

This application is based on applications Nos. JP2003-304518,JP2003-304519 and JP2003-337504 the content of which is incorporatedhereinto by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to wiring boards for mountingsemiconductor components such as semiconductor integrated circuit chips(LSI chips) used for information processing devices such as computers.

In particular, the present invention relates to a wiring board with adecoupling capacitor used as a power supply provided in the vicinity ofa semiconductor component, which allows the semiconductor component tooperate stably and speedily, and a semiconductor device comprising thewiring board and semiconductor component mounted thereon.

2. Description of the Related Art

Conventionally, in order to operate a semiconductor component speedilyand stably, studies have been devoted to stabilizing supply potentialand ground potential to the semiconductor component by disposing theso-called decoupling capacitor in the vicinity of the semiconductorcomponent so as to stably supply power to the semiconductor componentand suppress power supply noise.

As the wiring distance for electrically connecting the decouplingcapacitor and semiconductor component lengthens, due to the resistanceand inductance that the wiring has, it becomes difficult to maintainpower supply potential and ground potential stably.

In order to dispose the decoupling capacitor in the nearest vicinity ofthe semiconductor component, there has been proposed a structure inwhich, for example, the wiring board is fabricated by a ceramicmultilayer technique, and the power supply wiring and ground wiringstacked among the dielectric layers are arranged in a sheet-like mannerso as to generate capacitance among them, and a decoupling capacitor isdisposed inside the wiring board.

However, although the approach for forming a decoupling capacitor byutilizing conductive layers and dielectric layers allows the wiringdistance to be shortened, because of small dielectric constant of thedielectric layers, it has the drawback that the capacitance isinsufficient compared to when a chip capacitor is used.

Also, there is an existing method in which a chip capacitor is disposedon the back side of the semiconductor component-mounting area of thewiring board to shorten the wiring distance by wiring that penetratesthe wiring board.

In this method in which electrical connection is made by the wiring thatpenetrates the wiring board, while capacitance is sufficient because ofthe use of the chip capacitor, the wiring distance is prolonged by thethickened wiring board and inductance of the wiring inside the wiringboard becomes too great to be negligible.

In order to further shorten the wiring distance, there have beenproposed structures including the following: a structure in which a chipcapacitor is buried inside the wiring board; a structure in which a chipcapacitor is embedded in a cavity formed in the surface of the wiringboard; and further, a structure in which a chip capacitor is disposed ina gap between the wiring board and a semiconductor component mountedthereon.

However, when the structure in which the chip capacitor is buried insidethe wiring board is employed, peeling, cracking or break due todifference in thermal expansion coefficient between the buried chipcapacitor and the material of the wiring board around the chipcapacitor, and break due to clearance caused by insufficient machiningaccuracy on the wiring board and chip capacitor would occur.

Also, when the structure in which the chip capacitor is embedded in thecavity formed on the surface of the wiring board, because the bottomsurface of the cavity for embedding the chip capacitor reaches insidethe wiring board, the structure does not allow the capacitor to directlyconnect to a conductive wiring layer on the surface of the wiring board,and the connection is made via a conductive wiring layer on the backside of the wiring board. As a result, the wiring distance lengthens.

Although the method in which a chip capacitor is disposed in a clearancebetween the wiring board and a semiconductor component allows shortwiring distance and high mounting accuracy, space for inserting the chipcapacitor between the wiring board and the semiconductor component isnecessary. The distance of this needs to be at least greater than thethickness of the chip capacitor, which is considerably large as comparedto the height of a solder bump in the currently mainstream flip-chipmounting. Thus, realistically, inserting a chip capacitor is difficult,and this method can be applied to only limited applications that permita large bump pitch.

It is an object of the present invention to provide a wiring board and asemiconductor device capable of effectively and stably supplying powerand suppressing power supply noise that are necessary for stablyoperating semiconductor components.

BRIEF SUMMARY OF THE INVENTION

A wiring board according to the present invention comprises a coresubstrate, a build-up layer formed on at least one side of main surfacesof the core substrate, which comprises wiring conductor layers andinsulation layers alternately stacked therein, a chip-type decouplingcapacitor disposed within a cavity that is formed in the build-up layer,the capacitor having electrode terminals on an upper surface thereof anda connection portion on a back surface thereof that is connected to oneof the wiring conductor layers on a bottom surface of the cavity.

A semiconductor device according to the present invention comprises thewiring board and a semiconductor component mounted thereon.

The wiring board and semiconductor device with this structure have thecapacitor accommodated in the cavity and allow the electrode terminalson the upper surface of the capacitor to be directly connected to thesemiconductor component mounted on the wiring board, which enables thedecoupling capacitor to be connected to a semiconductor component withlow resistance and low inductance. Accordingly, rapid charge transferbetween the capacitor and semiconductor component is enabled, andmalfunctions of the semiconductor component due to instability of powersupply voltage can be prevented. In addition, power supply noise can beeffectively suppressed.

When the upper end of the electrode terminals on the upper surface ofthe capacitor is made flush with the upper end of the installationelectrode terminals for mounting the semiconductor component provided onthe build-up layer, the semiconductor component and the capacitor can bedirectly connected only by mounting the semiconductor component on thewiring board.

When the connection portion comprises electrode terminals provided onthe back surface of the capacitor, the connection between the capacitorand the wiring board can also be made with low resistance and lowinductance, allowing rapid charge transfer from the power supply to thecapacitor. As a result, malfunctions of the semiconductor component dueto instability of the power supply voltage can be prevented.

There is also a structure in which no electrode terminals are present onthe back surface of the capacitor, and the back surface of the capacitorand the bottom surface of the cavity are connected by an adhesive layer.

In cases where the adhesive layer is employed, it is preferable that theadhesive layer comprises a material that melts by heating. This isbecause when the semiconductor component is mounted on the wiring board,the adhesive layer is melted by heat, enabling self-alignment betweenthe capacitor and the semiconductor component. Accordingly, even if themachining accuracy on the capacitor is low, required positioningaccuracy with respect to the semiconductor component can be secured andoccurrence of contact failure of the capacitor can be prevented. Inaddition, since there is no need for jigs for positioning from outside,the mounting cost can be reduced. Furthermore, even if the thermalexpansion coefficient of the capacitor embedded in the cavity and thatof the build-up layer around the capacitor differ, peeling, cracking orbreak does not occur, and break or the like caused by insufficientmachining accuracy on the wiring board and capacitor does not occur.

In order to ensure the self-alignment, the melting point of theforegoing material is preferably lower than that of the metal materialused for mounting the semiconductor component on the wiring board.

Alternatively, the adhesive layer may comprise a material thatdisappears by heating. This is because self-alignment between thecapacitor and the semiconductor component is accomplished bydisappearance of the adhesion layer caused by heat.

The foregoing material preferably has a boiling point lower than themelting point of the metal material used for mounting the semiconductorcomponent on the wiring board.

When the adhesive layer disappears, a space is generated between theback surface of the capacitor and the wiring conductor layer on thebottom surface of the cavity in the semiconductor device according tothe present invention. The space is caused to be generated by thedisappearance of the adhesive layer that has been present between theback surface of the capacitor and the wiring conductor layer in thebottom surface of the cavity due to heating.

A wiring board according to the present invention further comprises asurface wiring layer for electrically connecting the electrode terminalsof the capacitor to the wiring conductor layer of the build-up layer,the surface wiring layer comprising wiring conductor layers andinsulation layers alternately stacked therein and installation electrodeterminals for mounting the semiconductor component provided at aposition above the capacitor, and a semiconductor device according tothe present invention comprises the wiring board with the foregoingstructure on which a semiconductor component is mounted.

The wiring board and the semiconductor component of the structure aboveare arranged such that the capacitor is accommodated in the cavity ofthe build-up layer through the surface wiring layer which is provided onthe upper surfaces of the build-up layer and the capacitor, and thesemiconductor component is mounted on a position immediately above thecapacitor in the surface wiring layer. Accordingly, the electrodeterminals of the capacitor can be connected to the semiconductorcomponent mounted on the surface wiring layer through the wiringconductor layers in the surface wiring layer in a short distance. Thisenables the capacitor and the semiconductor component to be connectedwith low resistance and low inductance. In addition, the connectionbetween the capacitor and the wiring board can be made through thewiring layers in the surface wiring layer in a short distance. As aresult, charge transfer from the power supply through the capacitor tothe semiconductor component can be accomplished rapidly, so thatmalfunctions of the semiconductor component due to instability of thepower supply can be prevented. Moreover, even if the thermal expansioncoefficient of the capacitor embedded in the cavity and that of thebuild-up layer around the capacitor differ, peeling, cracking or breakdoes not occur, and break or the like caused by insufficient machiningaccuracy on the wiring board and capacitor does not occur.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a wiring board according to thepresent invention in which cavities 120 are formed in a build-up layer130 a, and chip-type decoupling capacitors 121 are accommodated in thecavities 120.

FIG. 2 is a cross-sectional view of a semiconductor device fabricated bymounting a semiconductor integrated circuit chip 260 on a wiring boardaccording to the present invention.

FIG. 3 is a cross-sectional view of a wiring board in which a surfacewiring layer 130 c is provided on a build-up layer 130 a and decouplingcapacitors 121.

FIG. 4 is a cross-sectional view of a semiconductor device fabricated bymounting a semiconductor integrated circuit chip 260 on the wiring boardin FIG. 3.

FIG. 5 is a cross-sectional view of a wiring board in which cavities 120are formed in a build-up layer 130 a, and decoupling capacitors 121 areprovided in the cavities 120 through an adhesive layer 126 that ismelted by heating.

FIG. 6 shows a semiconductor device in which a semiconductor integratedcircuit chip 260 is mounted on the upper surface of the build-up layer130 a and decoupling capacitors 121 in FIG. 5.

FIG. 7 shows a semiconductor device in which decoupling capacitors 121are provided inside cavities 120 formed in a build-up layer 130 athrough an adhesive layer, and a semiconductor integrated circuit chip260 is mounted thereon. The adhesive layer has disappeared by heating.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, specific embodiments of the present invention will bedescribed in detail with reference to schematically illustrateddrawings.

Cross-sectional views of semiconductor wiring boards (hereinafter simplyreferred to as “wiring board”) provided with a capacitor of the presentinvention are shown in FIGS. 1, 3, and 5. Cross-sectional views ofsemiconductor components with a semiconductor integrated circuit chip ona wiring board are shown in FIGS. 2, 4 and 6. To avoid repetitiveexplanations, like components in different drawings are designated bythe same reference symbols.

The wiring board shown in FIG. 1 comprises a core substrate 110 servingas base and a build-up layer 130 a including wiring conductor layers andinsulator layers alternately stacked thereon.

The build-up layer 130 a is formed with cavities 120 on whose bottomsurfaces decoupling capacitors (hereinafter, simply referred to as“capacitor”) 121 are disposed. The capacitor 121 is a thin and flat chipprovided with electrode terminals to be connected to a semiconductorintegrated circuit chip on its top surface, and electrode terminals tobe connected to the build-up layer 130 a on its back surface.

The semiconductor component shown in FIG. 2 comprises the wiring boardshown in FIG. 1, and a semiconductor integrated circuit chip 260 isplaced on the electrode terminals on the top surfaces of the capacitors121 and the build-up layer 130 a, in which the semiconductor integratedcircuit chip 260 is electrically connected to the capacitors 121.

As shown in FIG. 1, the wiring board according to the present inventioncomprises a core substrate 110, a build-up layer 130 a formed on thesurface side of the wiring board, and a build-up layer 130 b formed onthe back side of the wiring board. The build-up layer 130 a on thesurface side of the wiring board wiring includes conductor lines 132(132 a, 132 b, 132 c, 132 d) constituting a first wiring conductor andinterlayer insulation layer 131 (131 a, 131 b, 131 c). The build-uplayer 130 b on the back side of the wiring board has a constructionsimilar to that of the build-up layer 130 a on the surface side of thewiring board. While the dielectric layers and electrode layers of thebuild-up layers 130 a and 130 b are drawn as they consist of 3-4 layersin FIG. 1, actually the number of these layers is greater. In thebuild-up layer 130 a on the surface side of the wiring board, thecavities 120 for accommodating the capacitors 121 are formed.

The material for the core substrate 110 may be an inorganic materialsuch as ceramics, AlN or the like, or a resin material generally usedfor printed wiring boards including glass epoxy resin-impregnated basematerial, phenol resin-impregnated base material or the like. Thematerial for the interlayer insulation layers 131 may be a thermosettingresin such as epoxy-based resin, thermoplastic resin, photosensitiveresin, a composite of thermosetting resin and thermoplastic resin, acomposite of photosensitive resin and thermoplastic resin or the like.

As the material for the wiring conductor layer 132, commonly usedconductor materials such as Cu, Al, Ni—Cu alloys, Cu—Al alloys may beused. The capacitor 121 comprises a plurality of dielectric layers andelectrode layers interposed among the dielectric layers. Through-holes124 penetrating through the main body of the capacitor 121 are formed inthe direction perpendicular to the main surfaces of the dielectriclayers and electrode layers. In the interior surface of the throughholes 124, through hole conductors 125 are formed. Electrode terminalsdrawn from both end faces of the through-hole conductors 125 are eachformed in the main surface on one side (upper main surface) and in themain surface of the other side (lower main surface).

Meanwhile, although FIG. 1 illustrates the capacitor 121 having three tofour dielectric layers and electrode layers, actually, the number ofthese layers is greater than this.

The capacitor 121 is disposed so that the upper main surface faces theopening (upper side) and the lower main surface faces the bottom surfaceof the cavity 120.

Via hole conductors 133 penetrating the interlayer insulation layer 131are formed in the interlayer insulation layer 131 of the build-up layer130 a, and the upper and lower wiring conductor layers 132 areelectrically connected through the via hole conductors. A solder resistlayer 151 comprising an insulator is formed on the wiring conductorlayer 132 that is formed in an upper most portion of the build-up layer130 a. The solder resist layer 151 is formed with small apertures, inwhich electrode terminals 152 connected to the wiring conductor layer132 d are buried.

Solder balls 123 used for mounting a semiconductor integrated circuitchip 260 are formed on the electrode terminals in the upper main surfaceof the body of the capacitor 121, and solder pads 122 used forconnection to the wiring conductor layer 132 a in the bottom surface ofthe cavity is formed on the electrode terminals in the lower mainsurface.

Solder balls 153 serving as a connection portion for mounting thesemiconductor integrated circuit chip 260 are formed on electrodeterminals 152 in the build-up layer 130 a.

In the wiring board, also on the opposite side of the surface on whichthe semiconductor integrated circuit chip 260 is mounted, the build-uplayer 130 b is provided as mentioned above.

The build-up layer 130 b is connected to the build-up layer 130 athrough interior through-hole wiring layers 111 formed in the coresubstrate 110. Electrode terminals 154 formed in the build-up layer 130b are electrically connected to a motherboard that is not shown throughsolder balls 155 serving as a connection portion.

In the wiring board of the present invention, the capacitor 121 isdisposed within the cavity 120, in which the bottom area of the cavity120 is made larger than the cross section area of the capacitor 121 tobe accommodated therein. This is because the machining accuracy for thecavities 120 is lower than the positioning accuracy for mounting thesemiconductor integrated circuit chip 260, and the position of thecapacitor 121 needs to be adjusted according to the wiring pattern ofthe wiring conductor layer 132 a on the bottom surface of the cavity120.

The depth of the cavity 120 is determined according to the thickness ofthe capacitor 121 to be accommodated therein. The depth of the cavity120 is preferably determined so that the upper main surface of thecapacitor 121 and the upper main surface of the solder resist layer 151(the upper end surface of the electrode terminals 152 in the build-uplayer 130 a) are flush with each other.

Meanwhile, the wiring board described so far may be embodied as a wiringboard in which no electrode terminals are present on the lower mainsurface of the body of the capacitor 121. In such a case, there are onlyelectrode terminals of the capacitor 121 that are connected to electrodeterminals of the semiconductor integrated circuit chip 260. In such acase, the adhesive used for bonding the back surface of the capacitorand the bottom surface of the cavity 120 together is preferably ofthermoplastic nature that permits self-alignment during the mounting ofa semiconductor component on the wiring board.

FIG. 2 is a cross-sectional view of a semiconductor device fabricated bymounting a semiconductor integrated circuit chip on a wiring boardaccording to the present invention.

Electrode terminals 261 provided on the back surface of a semiconductorintegrated circuit chip 260 are connected to electrode terminals 152 ofthe wiring board through solder balls 153 in the wiring board accordingto the present invention. The electrode terminals 261 provided on theback surface of the semiconductor integrated circuit chip 260 areelectrically connected to electrode terminals of capacitors 121 throughsolder balls 123. The capacitors 121 are connected to a wiring conductorlayer 132 a on the bottom surface of the cavities 120 through theforegoing solder pads 122.

In the semiconductor device of the present invention described above,the electrode terminals of the capacitors 121 can be directly connectedto the semiconductor integrated circuit chip 260 through the solder pads122. As a result, the resistance of the connection portions can besuppressed to a low level. In addition, because no routing is necessary,connections with low inductance can be made.

This enables rapid charge transfer between the semiconductor integratedcircuit chip 260 and the capacitors 121 mounted on the wiring board,allowing the capacitors 121 to absorb voltage variations that occur whena large amount of high frequency current flows in the semiconductorintegrated circuit chip 260, so that malfunctions due to instability ofthe power supply voltage of the semiconductor integrated circuit chip260 can be prevented.

While one capacitor 121 is disposed in each of the cavities 120 in thestructure of the wiring board described so far, it is possible todispose a plurality of capacitors 121 by increasing the bottom area ofeach cavity 120.

For example, by forming the bottom surface of the cavity 120 into theform of a long groove in plan view, a plurality of the capacitors 121can be aligned.

Referring now to FIG. 3, there is shown a wiring board comprising abuild-up layer 130 a on a core substrate 110, capacitors 121 providedwith electrode terminals on the upper surfaces thereof accommodatedwithin cavities 120 formed in the build-up layer 130 a, and a surfaceconductor layer 130 c provided on the upper surfaces of the build-uplayer 130 a and capacitors 121, the surface conductor layer 130 c havinga second wiring conductor that is electrically connected to the wiringconductor layers in the build-up layer 130 a and the electrode terminalsof the capacitors 121.

FIG. 4 shows a semiconductor device comprising the wiring board shown inFIG. 3, in which the semiconductor integrated circuit chip 260 isprovided on the surface wiring layer 130 c, and the semiconductorintegrated circuit chip 260 is electrically connected to the capacitors121 through the surface wiring layer 130 c.

As shown in FIG. 3, the wiring board according to the resent inventioncomprises a core substrate 110, a build-up layer 130 a formed on thesurface side of the wiring board a build-up layer 130 b formed on theback side of the wiring board, and a surface wiring layer 130 c formedon the build-up layer 130 a.

The build-up layer 130 a comprises a wiring conductor layer 132 (132 a,132 b, 132 c, 132 d) constituting a first wiring conductor and aninterlayer insulation layer 131 (131 a, 131 b, 131 c, 131 d). Thebuild-up layer 130 a is provided with cavities 120 for accommodating thecapacitors 121.

The construction of the capacitors 121 is the same as that explainedreferring to FIGS. 1 and 2, and therefore explanation thereof is notrepeated.

The surface wiring layer 130 c is provided on the build-up layer 130 aand comprises wiring conductor layers 143, 144 constituting a secondwiring conductor and interlayer insulation layers 141, 142 alternatelystacked on one another.

Via holes are formed in the interlayer insulation layers 131, 141, 142through which the upper and lower wiring conductor layers areelectrically connected to each other. Furthermore, a solder resist layer151 is formed on the surface wiring layer 130 c, which has apertures inwhich electrode terminals 152 are formed. Solder balls 153 used forconnection to the semiconductor integrated circuit chip 260 are formedon the electrode terminals 152.

The capacitors 121 mounted within the cavities 120 in the build-up layer130 a are connected to the wiring conductor layer 132 d constituting afirst wiring conductor layer of the build-up layer 130 a through asecond wiring conductor layer 143 in the surface wiring layer 130 c. Inaddition, the capacitors 121 are connected to the electrode terminals152 through the wiring conductor layer 144 in the surface wiring layer130 c.

Since the construction of a build-up layer 130 b on the opposite side ofthe surface on which the semiconductor integrated circuit chip 260 ismounted is the same as that explained referring to FIGS. 1 and 2, theexplanation thereof is not repeated.

FIG. 4 is a cross-sectional view of a semiconductor device fabricated bymounting a semiconductor integrated circuit chip 260 on a wiring board.

In this semiconductor device, electrode terminals 261 of thesemiconductor integrated circuit chip 260 and a second wiring conductorlayer 144 in a surface wiring layer 130 c of the wiring board areelectrically connected to each other through electrode terminals 152 andsolder balls 153. Since the second wiring conductor layer 144 in thesurface wiring layer 130 c is connected to capacitors 121 as mentionedbefore, the electrode terminals 261 of the semiconductor integratedcircuit 260 and the capacitors 121 are brought into an electricallyconnected state.

In the wiring board according to the present invention, the capacitors121 are disposed in the cavities 120. The cavities 120 are formed tohave a larger width than that of the capacitors 121. This is because themachining accuracy for the cavities 120 is lower than the positioningaccuracy for mounting the semiconductor integrated circuit chip 260, andthe positions of the capacitors 121 needs to be adjusted according tothe wiring pattern of the wiring conductor layer 132 a on the bottomsurface of the cavities 120.

The capacitors 121 can be fixed accurately to the positions within thecavities 120 by applying an adhesive to the bottom surface of thecavities 120 in accordance with the positions of the capacitors 121.Accordingly, it is possible to adjust the positions of the upperelectrode terminals of the capacitors 121 to the corresponding positionsof the wiring conductor layer 143 accurately.

As described so far, the wiring board according to the present inventionallows the electrode terminals of the capacitors 121 to be connected tothe semiconductor integrated circuit chip 260 located immediately abovethe electrode terminals through the surface wiring layer 130 c.Accordingly, connections with low resistance and low inductance can bemade. This enables rapid charge transfer between the semiconductorintegrated circuit chip 260 and the capacitors 121, so that even when alarge amount of high frequency current flows in the semiconductorintegrated circuit chip 260, the capacitors 121 can absorb the voltagevariations. As a result, malfunctions of the semiconductor integratedcircuit chip 260 can be prevented.

Moreover, it is made possible to prevent occurrence of contact failureof the capacitors due to insufficient mounting accuracy that has been asignificant problem from a practical point of view and to improve theyields in the manufacture of products.

FIG. 5 shows a wiring board comprising a core substrate 110 and abuild-up layer 130 a provided thereon that includes wiring conductorlayers and insulation layers alternately stacked on each other.Capacitors 121 provided with electrode terminals on their upper surfacesare disposed within cavities 120 formed in the build-up layer 130 athrough an adhesive layer 126 that melted or evaporated by heating.

FIG. 6 shows a state where a semiconductor integrated circuit chip 260is mounted on upper surfaces of the build-up layer 130 a and capacitors121 of the wiring board.

FIG. 7 is a cross-sectional view of a semiconductor device where theadhesive layer 126 has disappeared by heating after the mounting of thesemiconductor integrated circuit chip 260.

As shown in FIG. 5, the wiring board according to the present inventioncomprises the core substrate 110, the build-up layer 130 a formed on thesurface side of the wiring board and a build-up layer 130 b formed onthe back side of the wiring board. The build-up layer 130 a has cavities120 for accommodating the capacitors 121.

The construction of the build-up layer 130 a is the same as thatexplained referring to FIGS. 1 and 2, and therefore the explanationthereof is not repeated here.

Each capacitor 121 comprises dielectric layers and electrode layersformed in such a manner that they are interposed among the dielectriclayers. A couple of electrode terminals drawn from the electrode layersgather on a surface of the capacitor 121 on one side (the uppersurface). The capacitor 121 is disposed so that the upper surface havingthe couple of the electrode terminals faces the opening (the uppersurface) of the cavity 120.

In the wiring board according to this embodiment, while one or aplurality of the capacitors 121 are disposed in the cavity 120, thebottom profile of the cavity 120 is designed to be wider than the crosssectional profile of (the bottom of) the capacitor 121 accommodatedtherein.

A difference between the construction of the wiring board of the presentembodiment and those of the wiring board shown in FIGS. 1-4 is that noelectrode terminals are present on the back surfaces of the capacitors121.

Instead, the capacitors 121 are attached by applying an adhesive to thebottom surfaces of the cavities 120 in accordance with the positions ofthe capacitors 121. The layer formed of the adhesive is referred to as“adhesive layer 126”.

The positional accuracy of the capacitors 121 within the cavities 120 atthe time of the attachment of the capacitors 121 to the bottom surfacesof the cavities 120 is lower than the accuracy required for mounting thesemiconductor integrated circuit chip 260. In the present invention, thelow positional accuracy is compensated by the self-alignment effectdescribed later.

FIG. 6 is a cross-sectional view showing a state in which asemiconductor integrated circuit chip 260 is mounted on a wiring boardaccording to the present invention. Electrode terminals 261 provided onthe back surface of the semiconductor integrated circuit chip 260 areconnected to electrode terminals 152 of the wiring board through solderballs 153. The electrode terminals 261 provided on the back surface ofthe semiconductor integrated circuit chip 260 are electrically connectedto electrode terminals on the upper surfaces of capacitors 121 throughsolder balls.

The electrode terminals of the capacitors 121 mounted on the wiringboard are connected to the electrode terminals of the mountedsemiconductor integrated circuit chip 260 with high mounting accuracyowing to the self-alignment during the process of mounting semiconductorintegrated circuit chip 260.

Now, this will be described in detail. The capacitors 121 are attachedto the bottom surfaces of the cavities 120 by means of an adhesive layer126 at a time before the mounting of the semiconductor integratedcircuit chip 260. In this state, by mounting the semiconductorintegrated circuit chip 260 on the wiring board, the electrode terminals261 of the semiconductor integrated circuit chip 260 are brought intocontact with the electrode terminal of the wiring board so that theelectrode terminals 261 of the semiconductor integrated circuit chip 260are brought into contact with the electrode terminals of the capacitors121. In this state, the positions of the electrode terminals 261 of thesemiconductor integrated circuit chip 260 and the electrode terminals ofthe capacitors 121 are not necessarily coincide with each otheraccurately.

Subsequently, heating is carried out to melt the solder balls 123 and153. The adhesive layer 126 is brought into a molten state by this heat,and the capacitors 121 are in a state that allows the capacitors 121 tomove in any direction in the horizontal plane. Accordingly, the coupleof electrode terminals on the upper surface of each of the capacitors121 are attracted to positions immediately under the electrode terminals261 of the semiconductor integrated circuit chip 260 by surface tensionof the molten solder 123, by which the positions of the electrodeterminals 261 of the semiconductor integrated circuit chip 260 and theelectrode terminals of the capacitors 121 are adjusted correctly. As aresult, the “self-alignment” is accomplished.

Judging from the discussion above, the adhesive layer 126 needs to bebrought into a complete molten liquid state at least at the temperaturefor the solder reflow carried out when the semiconductor integratedcircuit chip 260 is mounted on the wiring board.

Because of the foregoing structure of the semiconductor device, thecapacitors 121 can be connected to the semiconductor integrated circuitchip 260 with low resistance and low inductance.

Furthermore, in the process of heating for melting the solder afterplacing the semiconductor integrated circuit chip 260 on thepredetermined position of the wiring board, the capacitors 121 can beconnected to the semiconductor integrated circuit chip 260 with accuratepositional coincidence. Accordingly, it is possible to prevent theoccurrence of contact failure of capacitors due to insufficient mountingaccuracy that has been a practically significant problem. In addition,because there is no need for jigs for adjusting the position of thecapacitors from outside, it is possible to reduce the mounting cost.

EXAMPLE 1

The wiring board shown in FIGS. 1 and 2 was produced. The productionprocess was as follows.

(1) A glass epoxy resin-impregnated base material was used for the coresubstrate 110. Prior to the formation of the build-up layer 130 a′, thecore substrate 110 was provided with holes for the through-holes bydrilling or laser machining. It is also possible to carry out besmear bya plasma treatment when the need arises.

(2) Subsequently, a copper-plated film was formed on the surface of thecore substrate 110 by electroless copper plating. Then, the whole of thecore substrate 110 was dipped in the electroless copper plating liquidto further form a copper-plated film using the foregoing copper-platedfilm as the electrode.

Subsequently, a photosensitive dry film is attached to the surface ofthe aforementioned copper-plated film, which was then subjected tomasked exposure followed by development with an alkali solution so thata resist-plated film with a predetermined pattern was formed.

Then, the whole of the core substrate 110 was dipped in the electrolesscopper plating liquid to form a copper-plated film using the foregoingcopper-plated film as the electrode. Subsequently, the copper-platedfilm beneath the resist-plated film was processed by etching with use ofa sulfuric acid/hydrogen peroxide mixture for dissolving and removalthereof, thereby forming the wiring conductor layer 132 a and thethrough-hole interior surface wiring layers 111 with predeterminedpatterns. At the same time, a wiring pattern to which the solder pads122 of the capacitors 121 are connected later was also formed on thewiring conductor layer 132 a. Although a diluted aqueous sodiumhydroxide solution was used as the foregoing alkaline solution, otheralkaline solutions such as an aqueous solution of potassium hydroxidemay be used.

The wiring conductor layer 132 a was formed to be thicker than otherwiring conductor layers 132 so that it functions as a stopper layerduring the laser machining for forming cavities described later.

Meanwhile, any of the wiring conductor layers 132 that are successivelyformed in later processes may be used as the stopper layer for the lasermachining depending on the required depth of the cavities 120. In thiscase, it should be formed to be thicker than other wiring conductorlayers 132 and a wiring pattern to which the solder pads 122 of thecapacitors 121 are connected should be formed in any of the wiringconductor layers 132 that is exposed on the bottom surfaces of thecavities 120.

Subsequently, an etch solution was sprayed on the both surfaces of thesubstrate so as to roughen the surface of the copper film as a wiringconductor layer and the surface of the through-hole 111 lands.Alternatively, a surface roughening treatment with argon plasma may becarried out.

Thereafter, a resin filler composed mainly of an epoxy-based resin wasinjected into the through-holes 112 and then dried. The resin filler maybe a thermosetting resin, thermoplastic resin, UV-hardening resin or thelike. However, a thermosetting resin is preferably used because of easeof handling.

(3) Then, the interlayer insulation layer 131 a was formed using anepoxy-based resin film that is a thermosetting resin by vacuum weldinglamination while raising the temperature.

Subsequently, openings for via holes were formed in the interlayerinsulation layer 131 a by laser beam cutting with use of a pulsed CO₂gas laser.

Also there is another method for forming the interlayer insulation film131 a, which uses a printer to coat a resin such as a thermosettingresin, thermoplastic resin, photosensitive resin, a composite includinga thermosetting resin and a thermoplastic resin, a composite including aphotosensitive resin and thermoplastic resin or the like. In addition,instead of laser beam cutting, an exposure and development process canbe used for formation of the openings. Also, it is possible to carry outbesmear using oxygen plasma when the need arises.

(4) Then formation of a wiring conductor layer was again carried out.First, a copper-plated film was formed on the surface of the interlayerinsulation film 131 a by electroless copper plating. Instead of thecopper film formed by electroless copper plating, a Ni—Cu alloy filmdeposited by sputtering may also be used. A photosensitive dry film wasapplied to this film, which is followed by photomask exposure anddevelopment with diluted sodium hydroxide to form a resist-plated film.Subsequently, an electroplated copper film with a predetermined patternwas formed by electroplating. After the resist film was peeled off andremoved with a diluted sodium hydroxide aqueous solution, theelectroplated copper film under the resist film was etched with asulfuric acid/hydrogen peroxide mixture for dissolving and removalthereof, thereby forming a wiring conductor layer 132 b comprising anelectroplated copper film.

(5) Subsequently, the interlayer insulation film 131 b was formed. Inthe same way as the formation of the foregoing interlayer insulationfilm 131 a, a thermosetting resin film was used and vacuum weldinglamination was carried out while raising the temperature. Then, openingsfor via holes were formed in the interlayer insulation layer 1311 b bylaser beam radiation.

(6) Thereafter, by repeating the foregoing processes of forming wiringconductor layer and interlayer insulation layer, the wiring conductorlayer 132 c, interlayer insulation layer 131 c, wiring conductor layer132 d and wiring conductor layer 132 d were successively formed.Meanwhile, the build-up layer 130 a can be formed with any number oflayers by repeating this process several number of times.

(7) By radiating the build-up layer 130 a produced in this way withlaser beams, the cavities 120 for accommodating the capacitors 121 wereformed. In this process, the areas of the formed cavities 120 were madelarger than the required size by about 50 μm. In determining this, thepositioning accuracy and profile accuracy of the laser machining weretaken into consideration.

(8) Thereafter, solder electrode terminals (the so-called “ball gridarray”) were formed with a grid-like pattern on the upper surface of thebuild-up layer 130 a. First, the solder resist layer 151 having openingsin the areas corresponding to the solder electrode terminals were formedby screen printing. Alternatively, a process of applying aphotosensitive solder resist followed by photomask exposure may be usedto accomplish the patterning.

Subsequently, the wiring board was dipped in an electroless nickelplating liquid for 20 minutes to form a nickel-plated film on theopenings, and it was further dipped in an electroless gold platingliquid to form a gold-plated film thereon, by which the solder pads 152were formed.

Thereafter, solder paste was printed on the solder pads 152, and after areflow process, the solder balls 153 were formed. However, bottom areasof the cavities 120 were not printed with the solder paste.

(9) In the last step, the capacitors 121 were disposed in accordancewith the positions of the wiring pattern on the bottom areas of thecavities 120. The capacitors 121 were fixed to and mounted on the wiringboard through a reflow process. It is also possible to inject athermosetting resin into the cavities 120 after the mounting and thenheat cure the resin so that the capacitors 121 are completely fixed.However, this thermosetting resin should not cover the upper mainsurfaces of the capacitors 121 where electrode terminals of thecapacitors 121 are present. The thermosetting resin may comprise epoxyresin, phenol resin, polyimide, triazine resin or the like. Thethermosetting resin preferably has a thermal expansion coefficient thatis a middle value between those of the capacitors 121 and the coresubstrate 110. In order to adjust the thermal expansion coefficient,using a plurality of resins or impregnation with a filler may be apossible way.

(10) The wiring board according to the present invention was obtainedthrough the steps above.

The wiring board produced as described above allows the capacitors 121accommodated in the cavities 120 in the build-up layer 130 a to bedirectly connected to the wiring conductor layer 132 a on the bottomareas of the cavities 120. Accordingly, the capacitors 121 can beconnected to the wiring board with lower resistance and lower inductancethan those in the conventional technologies. As a result, when thesemiconductor integrated circuit chip 260 was operated continuously at ahigh frequency, voltage drop in the capacitors, which often occurs inthe conventional technologies, was not observed.

EXAMPLE 2

Subsequently, the wiring board shown in FIGS. 3 and 4 was produced. Theproduction process thereof will be described referring to FIGS. 3 and 4.The production steps that are the same as the steps in the example ofFIGS. 1 and 2 are omitted as far as possible, and the stepscharacteristic of the present example 2 are described in detail.

First, the core substrate 110 having holes for through-holes wasfabricated as in the example 1. Then, the wiring conductor layer 132 acomprising a copper film and the through-hole interior surface wiringlayers 111 were formed in the surface of the core substrate 110. Then,the surface of the copper film and the surfaces of the through-hole 111lands were roughened, and a resin filler was injected into thethrough-holes 112.

The wiring conductor layer 132 a functions also as stopper layer for thelaser machining for cavity formation described later. Any of the wiringconductor layers 132 that are hereinafter successively stacked may beused as the stopper layer in accordance with the required depth of thecavities 120.

Subsequently, the interlayer insulation layer 131 a, the wiringconductor layer 132 b, the interlayer insulation layer 131 b, the wiringconductor layer 132 c, interlayer insulation layer 131 c, wiringconductor layer 132 d were alternately and successively formed.

The build-up layer 130 a comprising the interlayer insulation layers 131and wiring conductor layers 132 formed in the foregoing way was providedwith the cavities 120 for accommodating the capacitors 121 by lasermachining. In this step, the areas of the cavities 120 formed were madelarger than the required size by about 50 μm.

Thereafter, an adhesive was applied using a printer to the positions onthe bottom surfaces of the cavities where the capacitors 121 were to bedisposed. Meanwhile, instead of the application of the adhesive, pottingmay be carried out. The thermal expansion coefficient of the adhesive ispreferably at a middle value between those of the capacitors 121 andcore substrate 110.

Subsequently, the capacitors 121 were disposed on and fixed to thepositions in the bottom surfaces of the cavities 120 to which theadhesive was applied.

Thereafter, gaps between the capacitors 121 and cavities 120 were filledwith a thermosetting resin, which was heat cured so that the capacitors121 were completely fixed. Here, the application of thermosetting resinwas intended not to cover the surfaces where the electrode terminals ofthe capacitors 121 were present. The thermosetting resin preferablycomprises epoxy resin, phenol resin, polyimide, triazine resin or thelike. Preferably, the thermosetting resin has a thermal expansioncoefficient that is a middle value between those of the capacitors 121and the core substrate 110. In order to adjust the thermal expansioncoefficient, using a plurality of resins or impregnation with a fillermay be a possible way.

Then, with the capacitors 121 fixed to the cavities 120, the interlayerinsulation layer 141 was formed on the wiring conductor layer 132 d. Bythe same formation process as described above, the interlayer insulationlayer 141 was formed by vacuum welding lamination using an epoxy-basedresin film that is a thermosetting resin while raising the temperature.Openings for via holes for connection to the wiring conductor layer 132d were provided at the predetermined positions in the interlayerinsulation layer 141.

Subsequently, the wiring conductor layer 143 for connecting theelectrode terminals of the capacitors 121 to conduction circuits of thebuild-up layer 130 a was formed over the interlayer insulation layer.Then, the interlayer insulation layer 142 and the wiring conductor layer144 were successively formed. The wiring conductor layer 144 is thelayer for providing connection bumps for mounting the semiconductorintegrated circuit chip 260.

Through the steps above, the surface wiring layer 130 c was fabricated.

Subsequently, solder electrode terminals (the so-called “ball gridarray”) were, formed with a grid-like pattern on the surface wiringlayer 130 c. First, the solder resist layer 151 was formed by screenprinting. Alternatively, a process of applying a photosensitive solderresist followed by photomask exposure may be used to accomplish thepatterning. Subsequently, the wiring board was dipped in an electrolessnickel plating liquid for 20 minutes to form a nickel-plated film on theopening areas of the solder resist layer 151, and it was further dippedin an electroless gold plating liquid to form a gold-plated filmthereon, by which the solder pads 152 were formed.

In the following step, solder paste was printed on the solder pads 152,and after a reflow process, the solder balls 153 were formed.

The wiring conductor layer 143 enables the electrode terminals of thecapacitors 121 to be connected to the wiring conductor layer 132 d ofthe build-up layer 130 a with low resistance and low inductance, andenables rapid charge transfer to the capacitors 121.

The wiring conductor layer 144 is connected to the electrode terminalsof the capacitors 121 with low resistance and low inductance, andelectric charges are supplied from the capacitors 121 to thesemiconductor integrated circuit chip 260 through the solder balls 153in a low resistance and low inductance condition.

The wiring pattern for laying out the solder bumps 152 of the foregoingwiring conductor layer 144 has high accuracy and a narrow pitch. On theother hand, the wiring pattern for laying out the wiring conductor layer143 connected to the electrode terminals of the capacitors 121 has awide pitch and takes a large area for the connection areas. The reasonfor the difference in pitch and size between the wiring patterns is asfollows: despite the requirement for high accuracy for mounting thesemiconductor integrated circuit chip 260, since the capacitors 121 aredisposed with low positional accuracy as described above, the connectionareas are widely designed for anticipated positional differences so thatthe connections are not misaligned.

The wiring board produced in this way had resistance and inductance aslow as those in the prior art, and contact failure of the capacitorsafter the mounting of the semiconductor integrated circuit chip 260,which often occurs to the wiring boards in the conventionaltechnologies, was not observed in the wiring board of the presentinvention. In addition, even when the semiconductor integrated circuitchip 260 was continuously operated at a high speed, voltage drop of thecapacitors, which often occurs in the conventional technologies, was notobserved.

EXAMPLE 3

Subsequently, the wiring board shown in FIGS. 5, 6 and 7 was produced.The production process thereof will be described. The production stepsthat are the same as the steps in the example of FIGS. 1 to 4 areomitted as far as possible, and the steps characteristic of the presentexample 3 are described in detail.

Referring to FIG. 5, the core substrate 110 having holes forthrough-holes was fabricated. Then, the wiring conductor layer 132 acomprising a copper film formed on the surface of the core substrate 110and the through-hole interior surface wiring layers 111 were formed.Then, the surface of the copper film and the surfaces of thethrough-hole lands were roughened, and a resin filler was injected intothe through-holes 112.

The wiring conductor layer 132 a functions also as stopper layer duringthe laser machining for cavity formation as described later. Any of thewiring conductor layers 132 that are hereinafter successively stackedmay be used as the stopper layer in accordance with the required depthof the cavities 120.

Subsequently, the interlayer insulation layer 131 a, the wiringconductor layer 132 b, the interlayer insulation layer 131 b, the wiringconductor layer 132 c, interlayer insulation layer 131 c, wiringconductor layer 132 d were successively formed.

The build-up layer 130 a comprising the interlayer insulation layers 131and wiring conductor layers 132 formed in the foregoing way was providedwith the cavities 120 for accommodating the capacitors 121 by lasermachining. In this step, the areas for forming the cavities 120 weremade larger than the required size by about 50 μm. In determining this,the positioning accuracy and profile accuracy of the laser machiningwere taken into consideration.

Thereafter, an adhesive was applied using a printer in accordance withthe positions of the capacitors 121 in the bottom surfaces of thecavities 120. Meanwhile, instead of the application of the adhesive,potting may be carried out.

The adhesive material used was POM (Polyoxymethylene).

The adhesive material needs to be in a solid state at the peaktemperature of heating in the reliability test after the production ofthis wiring board, and in a completely molten state at the peaktemperature in the solder reflow process carried out when thesemiconductor integrated circuit chip 260 is mounted on this wiringboard. In addition, the melting point of the adhesive material ispreferably lower than the solidification temperature of the solder inorder to accomplish good self-alignment. Since the melting point of POMis 181° C. and the melting point of the solder is 220° C., the foregoingconditions are satisfied. Polypropylene (PP) having a melting point of180° C. may also be used as the material.

After the formation of the adhesive layer 126, the wiring board washeated to 200° C. to melt the adhesive layer 126, and then thecapacitors 121 were disposed at the positions in the bottom surfaces ofthe cavities 120 to which the adhesive material was applied. Then, thetemperature was gradually lowered to room temperature so that thecapacitors 121 were once fixed to the bottom surfaces of the cavities120.

Thereafter, a solder resist layer 151 having solder pads 152 was formedon the wiring conductor layer 132 d, and the solder balls 153 weredeposited on the solder pads 152.

Then, the semiconductor integrated circuit chip 260 was placed on thewiring board produced in the foregoing manner, and the solder was meltedby reflow, thereby mounting the semiconductor integrated circuit chip260 on the wiring board. The peak temperature for the reflow during themounting was 260° C.

Twenty four samples of semiconductor devices were fabricated in theabove described way, and electric properties between the capacitors 121and the semiconductor integrated circuit chip 260 were measured. Theelectric properties are the kind that can be obtained by measuring thepower supply voltage applied to the semiconductor integrated circuitchip 260 and the load current flowing into the loads that are connectedto the semiconductor integrated circuit chip 260.

As for the resistance and inductance characteristics, the measuredresistance and inductance were both as low as those in conventionaltechnologies that have a structure comprising chip capacitors embeddedin cavities formed on a surface of a wiring board for accommodating asemiconductor chip.

In addition, contact failure of capacitors 121 after the mounting of asemiconductor integrated circuit chip, which was often seen inconventional technologies, was not observed in the wiring board of thepresent invention.

This shows that the semiconductor integrated circuit chip 260 and thecapacitors 121 are completely electrically connected in the wiring boardof the present invention.

Furthermore, a wiring board in which 2,3-xylenol was used as anothermaterial for the adhesive layer 126 was produced.

After the adhesive layer 126 was formed on the bottom surfaces of thecavities 120, it was heated to 90° C., and then the capacitors 121 wereplaced at the positions in the bottom surfaces of the cavities 120 towhich the adhesive material as applied. Then the temperature wasgradually lowered to room temperature so that the capacitors 121 werecooled and fixed. The reason for the heating temperature lower than thatin the case of POM is that the melting point of 2,3-xylenol is 75° C. Inthe case where 2,3-xylenol was used, because of the boiling point 218°C. of 2,3-xylenol, 2,3-xylenol gradually evaporated during the solderreflow (the peak temperature during the solder reflow was 260° C.), andafter the solder was solidified, the adhesive layer 126 completelydisappeared.

The state where 2,3-xylenol disappeared is shown in FIG. 7. In thiscase, more complete self-alignment can be accomplished than in the caseof FIG. 6.

As other adhesive materials, isomers such as 2,5-xylenol(melting point:75° C., boiling point: 210° C.), 3,4-xylenol(melting point: 65° C.,boiling point: 225° C.), 3,5-xylenol (melting point: 65° C., boilingpoint: 220° C.) and mixtures thereof may be used.

When the samples were checked after the mounting of the semiconductorintegrated circuit chip 260, the adhesive layer disappeared in all ofthe 24 samples.

Measurements of the electric properties revealed that the samples showedresistances and inductances as low as those in conventional technologiesthat have a structure comprising chip capacitors embedded in cavitiesformed on a surface of a wiring board for accommodating a semiconductorchip.

In addition, contact failure of capacitors after the mounting of asemiconductor integrated circuit chip, which was often seen inconventional technologies, was not observed in the wiring board of thepresent invention. Accordingly, it seemed that the mounting of thecapacitors 121 of this example was accomplished also by self-alignment.

1. A wiring board comprising: a core substrate; a build-up layer formedon at least one side of main surfaces of the core substrate, whichcomprises wiring conductor layers and insulation layers alternatelystacked on each other; and a capacitor disposed within a cavity that isformed in the build-up layer; wherein the capacitor has electrodeterminals on an upper surface thereof and a back surface of thecapacitor has a connection portion that is connected to one of thewiring conductor layers on a bottom surface of the cavity.
 2. The wiringboard according to claim 1, wherein the upper end of the electrodeterminals on the upper surface of the capacitor is flush with the upperend of installation electrode terminals provided on the build-up layerfor mounting a semiconductor component.
 3. The wiring board according toclaim 1, wherein the connection portion comprises electrode terminalsprovided on the back surface of the capacitor.
 4. The wiring boardaccording to claim 1, wherein the connection portion comprises anadhesive layer for bonding the back surface of the capacitor to thewiring conductor layer on the back surface of the cavity.
 5. The wiringboard according to claim 4, wherein the adhesive layer comprises amaterial that is melted by heating.
 6. The wiring board according toclaim 5, wherein the material has a melting point lower than that of amaterial used for mounting the semiconductor component on the wiringboard.
 7. The wiring board according to claim 4, wherein the adhesivelayer comprises a material that disappears by heating.
 8. The wiringboard according to claim 7, wherein the material has a boiling pointlower than that of a material used for mounting the semiconductorcomponent on the wiring board.
 9. The wiring board according to claim 2,further comprising a surface wiring layer for electrically connectingthe electrode terminals of the capacitor to the wiring conductor layerof the build-up layer, the surface wiring layer comprising wiringconductor layers and insulation layers alternately stacked on each otherand installation electrode terminals for mounting the semiconductorcomponent at a position above the capacitor on the surface wiring layer.10. The wiring board according to claim 9, wherein the installationelectrode terminals are electrically connected to the electrodeterminals of the capacitor through the wiring conductor layers in thesurface wiring layer.
 11. The wiring board according to claim 9, whereinthe connection portion comprises an adhesive layer for bonding the backsurface of the capacitor to the wiring conductor layer on the bottomsurface of the cavity.
 12. A semiconductor device comprising a wiringboard and a semiconductor component mounted on the wiring board, thewiring board comprising a core substrate, a build-up-layer formed on atleast one side of main surfaces of the core substrate, which compriseswiring conductor layers and insulation layers alternately stacked oneach other, and a capacitor disposed within a cavity that is formed inthe build-up layer, wherein the capacitor have electrode terminals on anupper surface thereof, the upper ends of the electrode terminals of thecapacitor are made flush with the upper ends of installation electrodeterminals provided on the build-up layer for mounting a semiconductorcomponent, and the semiconductor component is connected to theinstallation electrode terminals of the build-up layer and the electrodeterminals of the capacitor.
 13. The semiconductor device according toclaim 12, further comprising a connection portion interposed between aback surface of the capacitor and one of the wiring conductor layers ona bottom surface of the cavity, the connection portion comprisingelectrode terminals provided on the back surface of the capacitor. 14.The semiconductor device according to claim 12, further comprising anadhesive layer bonding a back surface of the capacitor to one of thewiring conductor layers between the back surface of the capacitor andthe conductor electrode layer on the bottom surface of the cavity. 15.The semiconductor device according to claim 12, wherein a space ispresent between a back surface of the capacitor and one of the wiringconductor layers on a bottom surface of the cavity.
 16. Thesemiconductor device according to claim 15, wherein the space isgenerated as a result of disappearance of an adhesive layer interposedbetween the back surface of the capacitor and the wiring conductor layeron the bottom surface of the cavity by heating.
 17. A semiconductordevice comprising a wiring board and a semiconductor component mountedthereon, the wiring board comprising: a core substrate, a build-up layerformed on at least one side of main surfaces of the core substrate,which comprises wiring conductor layers and insulation layersalternately stacked therein, and a capacitor disposed within a cavitythat is formed in the build-up layer, the capacitor having electrodeterminals on an upper surface thereof; and a surface wiring layer forelectrically connecting the electrode terminals of the capacitor to thewiring conductor layers of the build-up layer, the surface wiring layercomprising wiring conductor layers and insulation layers alternatelystacked on each other, and installation electrode terminals for mountingthe semiconductor component provided at a position above the capacitor,wherein the semiconductor component is disposed on the surface wiringlayer.
 18. The wiring board according to claim 17, wherein theinstallation electrode terminals are electrically connected to theelectrode terminals of the capacitor through the wiring conductor layersin the surface wiring layer.